1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a related method of fabrication. More particularly, embodiments of the invention relate to a bipolar transistor and a related method of fabrication.
2. Description of Related Art
Using a complementary metal-oxide semiconductor (CMOS) fabrication technology, an n-channel MOS field effect transistor (MOSFET) and a p-channel MOSFET may be formed adjacent to each other on a semiconductor substrate. The steady development of the CMOS fabrication technology over the past several decades has resulted in a present ability to fabricate highly integrated, high performance semiconductor devices at low cost. CMOS devices are widely used to fabricate radio frequency (RF) circuits, RF system-on-chips (SoC), and many other devices.
Although the CMOS devices have very solid operating characteristics, they often do not satisfy the low noise requirements demanded by contemporary RF circuits and/or circuit elements. Low noise amplifiers (LNAs) and a voltage controlled oscillators (VCOs) are ready examples of RF circuits demanding low noise performance.
As compared with MOSFETs, bipolar transistors have low noise, wide linear gain, good frequency response, and high current drivability. In order to implement certain circuits or circuit functions, bipolar transistors are often formed on the same semiconductor substrate as CMOS devices. Indeed, in one common application, high-performance bipolar transistors are used to implement RF circuits and CMOS devices are used to implement associated logic circuits.
To enhance the operating speed of bipolar transistors, the base region needs to be narrowly formed so that carriers may move quickly from emitter to collector. Alternatively, the base region may be doped with a high concentration of conductive impurities in order to reduce the resistance of the base region. Generally, a very narrow base region is formed using an ion implantation process. However, it is very difficult to form an exceptionally narrow base region using conventional ion implantation processes.
Accordingly, the base regions of bipolar transistors are sometimes formed using methods that include an epitaxial technique. According to such epitaxial base formation techniques, a thin base region having a high doping concentration may be formed because dopant ions are added during the epitaxial growth process.
To increase the doping concentration of the base region for purposes of enhancing the operating speed, it is also necessary to increase the doping concentration of the corresponding emitter region in order to obtain high current gain. However, increasing the doping concentration of the emitter region causes a reduction in bandgap, resulting in decreased carrier injection efficiency and reduced emitter-base breakdown voltage. These trade-offs practically restrict the use of the foregoing techniques in attempts to improve the operating speed of bipolar transistors.
As a result, methods of forming a heterojunction between base and emitter have been proposed. Within such heterojunction structures the bandgap of the emitter is different from that of the base. To form the heterojunction, the base region is typically formed from silicon-germanium, which has a narrower bandgap than that of silicon. In the heterojunction structure, the emitter may emit carriers to the base with greater efficiency.
Figure (FIG.) 1 is a schematic sectional view of a heterojunction bipolar transistor disclosed, for example, in U.S. Pat. No. 6,251,738. In FIG. 1, reference numerals 10 and 18 indicate a silicon substrate and a collector, respectively. A p-type epitaxial silicon-germanium (Si—Ge) base 22 is grown on substrate 10. A p-type polysilicon base 36 is formed on Si—Ge base 22. Reference numerals 42 and 54 indicate spacers and a base contact, respectively. A reference numeral 44 indicates an n-type polysilicon emitter. Reference numerals 56 and 52 indicate an emitter contact and a collector contact, respectively. Within the foregoing conventional structure, polysilicon emitter 44 and polysilicon base 36 are electrically isolated from each other by spacers 42.
In addition, the top surface of polysilicon emitter 44 is relatively higher than that of the polysilicon base 36, thereby forming a large step between polysilicon emitter 44 and collector 18. Accordingly, the polysilicon emitter 44 whose top surface is relatively high may be over-etched when an insulating interlayer 50 is etched to form contact holes for emitter contact 56, base contact 54, and collector contact 52. Specifically, when a silicide layer is used to form a low resistance contact, the over-etching problem becomes even more serious. The silicide layer is formed relatively thinly on n-type polysilicon emitter 44 compared with p-type polysilicon base 36. Accordingly, the silicide layer formed on these elements may be particularly susceptible to over-etching. Consequently, a stable contact having low resistance is very difficult to form.
Furthermore, in the foregoing conventional structure, the process by which polysilicon base 36 and polysilicon emitter 44 are formed electrically isolated from each other is very complicated. That is, in order to form polysilicon base 36, epitaxial Si—Ge base region 22 is formed and then a polysilicon layer is deposited. Then, an etch-back process is used to expose epitaxial base region 22 through the polysilicon layer. A patterning process is then applied to the etched-back polysilicon base 36 to form a contact window 40 ultimately receiving polysilicon emitter 44. Then, spacers 42 are formed on sidewalls of contact window 40. Finally, another polysilicon layer is deposited and patterned to form polysilicon emitter 44.
FIG. 2 is a schematic sectional view of a bipolar transistor formed in accordance with a method such as the one disclosed, for example, in U.S. Pat. No. 6,744,080. In FIG. 2, reference numerals 2, 5, 9, 13 and 14 indicate a base, a base terminal, an emitter terminal, a base contact, and an emitter contact, respectively. Like the previous conventional example, emitter terminal 9 is relatively higher than base terminal 5, and the electrical isolation between emitter terminal 9 and base terminal 5 is achieved through a complicated fabrication process.
Accordingly, a bipolar transistor having enhanced operating speed but fabricated through a more simple process is required.